As will be appreciated by those skilled in the art, the performance of a high speed SRAM (static Random Access Memory) can be limited by the performance of its address decoders. In certain SRAM designs, as soon as a particular row of cells may be selected by the corresponding word line going high, the bit lines begin to develop a voltage based on the contents of the memory cells. The sooner the word line goes high, the better the read performance of the SRAM. Hence, speed up in the operation of the address decoders results in a better performance of the memory array.
CMOS logic may be often implemented in dynamic logic where circuits may be precharged in a precharge phase of clocking, and evaluated in an evaluate stage of the clocking.
Dynamic decode circuits may be synchronous logic circuits that generate an output depending upon a predetermined combination of inputs. Precharge devices may be characterized by two states, precharge and evaluate. In the precharge state, a node may be charged to a known or predetermined voltage level, for example high (near VDD). In the evaluate state, an array or “tree” of transistors may be given the opportunity to either discharge the node to a second known or predetermined voltage level, for example low (near VSS) or to allow the charge to persist. Each input signal may be connected, typically, to a gate of one or more of the transistors in the tree. The final charge on the output node may thereby be controlled by the particular values of the inputs and the way in which the transistors may be connected within the tree. The final voltage at the node, high or low, acts as the output of the dynamic decode circuits after being suitably buffered and, perhaps, inverted. The two states of a precharge device each correspond to one of the two logic states of a clock signal cycle to which the precharge device may be synchronized. Typically, a pfet precharge device precharges the node when the clock is low and evaluates the node when the clock is high.
Two common uses for precharge devices may be as decoders and as comparators. Decoders output a unique signal if and only if all of the bits of an input match a predetermined set of values. A decoder may thereby enable a particular write line in a matrix of memory cells if and only if an input memory address matches the predetermined address of a line of memory cells to which the decoder may be connected. Similarly, a comparator will output a unique signal if and only if two inputs, each containing multiple data bits, may be identical.
The particular way the inputs may be combined within the tree of a dynamic decode circuit determines the particular operating characteristics (function) and, hence, the particular name of the node. As described above, if the tree discharges the charged node if and only if the input bits match a single set of predetermined values, then the a dynamic decode circuit may be a decoder. Any Boolean function can be implemented as a dynamic decode circuit by constructing the tree such that the tree causes the precharge device to discharge when the Boolean function may be either true or false, as needed by the designer. Logically, it may be irrelevant whether a tree allows the charge in a dynamic decode circuit to persist when the Boolean function is true or to persist when the function is false.
Each dynamic decode circuit can be implemented in one of two logically equivalent ways. The two implementations correspond to a tree that discharges the charged node when the Boolean function is true and to a tree that discharges the charged node when the Boolean function is false. When a dynamic decode circuit discharges the node if the Boolean function is true, it may be said to “evaluate to the active state.” When the precharge device discharges the node if the Boolean function may be false, it may be said to “evaluate to the inactive state.” One of these implementations uses its inputs directly connected in a manner to describe a particular function. The second implementation uses the complements of the inputs and a second function. DeMorgan's law allows the designer to restructure the tree of the first function to produce a tree for the second function. The second function may be the first function's complement.
Although logically equivalent, each of the two possible implementations of a dynamic decode circuit has its own disadvantage. Specifically, the more transistors connected in series within the tree, the slower the performance of the dynamic decode circuit. This disadvantage may be typically associated with a dynamic decode circuit that discharges the charged node when its function is true. Conversely, a dynamic decode circuit that evaluates to the inactive state generates an output unacceptable to many types of circuits. This disadvantage may be typically associated with a dynamic decode circuit that discharges the charged node when its function is false.